-全网知识付费-后添加课程/DDR全面解析及实战/第七章 DDR Package and PCB Guidelines

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主页/后添加课程/DDR全面解析及实战/第七章 DDR Package and PCB Guidelines/

1.DDR Package and PCB Guidelines.mp4
10.Clock vs. Signal for Single Rank Implementation.mp4
11.Heavily Loaded Nets with 2T Clocking.mp4
12.Biasing DQS and DQS#.mp4
13.Selecting Termination Values.mp4
14.Terminating Daisy Chain or Fly-By Nets.mp4
15.Characteristic Impedance Varies with Crosstalk from Neighboring Signals.mp4
16.Packaging.mp4
17.Bond Wire vs. Flip Chip.mp4
18.Bond Wire Package Structure.mp4
19.Flip Chip Package Structure.mp4
2.DDR Signaling.mp4
20.Routing the Package - Planes.mp4
21.Package Connections and ViaBall Count.mp4
22.VDDQ vs VSSQ and VSS vs VSSQ Planes.mp4
23.Trace Routing Skew.mp4
24.Other routing rule is the same with PCB.mp4
25.Power Integrity and Package Selection.mp4
26.Package Power Network.mp4
27.Inductance and Resistance for different package.mp4
28.End.mp4
3.DDR Interface Signal Families.mp4
4.PCB Stack-Up.mp4
5.PCB Skew Control.mp4
6.Microstrip and Stripline.mp4
7.Skew Considerations.mp4
8.Spacing between Different Signal Groups.mp4
9.Traces should not be routed Across Splits.mp4

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